In the operation of certain semiconductor circuit devices, pullup and pulldown sense amplifiers (sense amps) detect and amplify a small charge stored within a memory cell. In general, two complementary digit lines are attached to a pullup sense amp and a pull down sense amp. At the beginning of a reading operation, both lines are at an equilibrate voltage Veq, which is generally between the potential of a voltage source used to operate the semiconductor device (VCC) and ground potential (0 volts). While Veq is changeable either intentionally or inadvertently through a defect, Veq is ideally equal to VCC/2 during non-test operations. This midpoint voltage is defined as DVC2.
One of the digit lines is coupled to a memory cell. The reading process involves a discharge from the memory cell to the corresponding digit line, which creates a slight difference in voltage between the two digit lines. This difference is then amplified by the sense amps: the digit line with the slightly lower voltage has its voltage further decreased by the pulldown sense amp, and the voltage of the other digit line is increased by the pullup sense amp. Once the voltage difference has been amplified, the digit lines can then be used to operate less sensitive circuitry.
Between reading cycles, it is necessary to return the complementary digit lines to Veq. This occurs during what is known as a precharge cycle, wherein equilibration transistors short the complementary digit lines together. Further, a signal having a potential of DVC2 is communicated from a DVC2 voltage generator to the shorted digit lines through a bleeder device.
Concerning the operation of the sense amps, it should be noted that pulling down the voltage of a digit line involves coupling the line to ground through a pulldown transistor. Because an entire row of digit line pairs often connects to the same pulldown transistor through a common node, the pulldown transistor will most likely have to draw current from one line of each of several pairs. In doing so, there is a risk that the transistor will become saturated with current and therefore become slower in pulling down the voltage of additional digit lines. This may lead to errors in reading, especially if an entire row of memory cells is storing logic 1's except for one cell storing a logic 0; for once the logic 0 is discharged, a slow pulldown may result in an improper reading of that logic 0 value.
One known way to solve this problem is to include an optional active area in the gate of the pulldown transistor. The increased size of the gate raises the threshold at which the pulldown transistor becomes saturated. However, one of ordinary skill in the art will appreciate that this solution requires a costly metal mask change. Further, any attempt to speed up the slowed pulldown raises other problems in reading, as disclosed in U.S. Pat. No. 5,042,011, by Casper, et al. The Casper '011 reference discloses that pulling down the common node too quickly may result in capacitive coupling between the sources and drains of the sense amp's transistors. During capacitive coupling, both digit lines in one sense amp are pulled down before the common node is pulled down low enough to turn on one of the sense amp transistors. When the sense amp finally turns on, it shorts out the capacitive coupling, bouncing the digit lines and, in the process, creates line noise that will interfere with the ability to read the data properly.
Early saturation and capacitive coupling could be avoided if one knew the margin—the difference in voltage between a logic 0 signal and a logic 1 signal—that the pulldown transistor was capable of accommodating. The only way to do so, as taught by the prior art, is to separate the pulldown transistor with a laser and probe the gate.
As an alternative to determining the sense amp's margin, one could simply test the sense amp's ability to operate at the given source voltage used in non-test operations. Prior art suggests entering a series of test data patterns into memory. Logic 1's are written to the cells of each memory array, with the exception of one column of logic 0's. As a result, each row contains only one cell storing a logic 0, thereby creating the most likely circumstance for an error in reading the data. The data in the array is then read and checked for errors. Once the first group of test data has been processed, a second sample of test data is entered with the logic 0's written to the next column. This process repeats until a logic 0 has been written to and read from every cell in any given row in the memory array. The results will indicate the pulldown transistor's ability to read data accurately. The problem with this process, however, is that it is time consuming to enter multiple samples of test data.
Thus, there is a need in the art for a quicker circuit and method for testing the capabilities of a sense amp. Further benefit would be derived if this test could indicate the margin of the sense amp's pulldown transistor.
In addition to inadequate pulldown transistors, other problems, such as defects arising during the processing of semiconductor devices, may contribute to reading errors. Various techniques involving equilibration of the complementary digit lines can be used during testing to detect these problems. For example, occasionally a digit line will inadvertently have a short to ground. As a result, the potential of that digit line will leak towards 0 volts. To detect this problem, prior art teaches extending the time for the precharge cycle during a test mode. If the short has a low enough resistance, the short will overcome the charging ability of the DVC2 voltage generator, which remains coupled to the digit lines, and Veq of the digit lines will decrease. Thus, a longer precharge cycle allows Veq to lower even further. As a result, line noise is more likely to register as a logic 0 discharge on the digit line when in fact the storage cell contains a logic 1 and has not yet discharged. Alternatively, assuming that a logic 1 is properly discharged and sensed, a reading error is still likely: Veq may be so low due to the short that the pullup sense amp may not be able to pull up the digit line's voltage in time to register as a logic 1 for purposes of driving external circuitry. Increasing the likelihood of error is desirable in the test mode, as it helps to identify errors that would affect non-test operations. Further, a reading error occurring after this extended precharge cycle will indicate the nature of the defect—in this case a short in at least one of the digit lines. However, this testing process can be time consuming. As an example, a 64 meg DRAM having a 16 meg×4 configuration requires approximately 170 seconds to carry out this test. It would be a benefit to the art to have a faster way to test for this problem.
A second problem that could be detected by altering the equilibration rate of the digit lines involves a short between the cell plate and the digit line. The typical technique for discovering this problem is to initiate a long RAS (Row Address Strobe) low signal. During the low RAS, the digit lines are not equilibrated. Rather, they are charged to their complementary voltage levels. Ideally, once the low RAS ends and the lines are shorted, both digit lines should approach a Veq level of DVC2. However, a short between one of the digit lines and the cell plate will allow the DVC2 generator 68 to change that digit line's voltage during the RAS low period. Thus, once the lines are shorted, their respective voltages will meet at a different Veq level. This will affect the margin between Veq and the voltage corresponding to one of the logic values and thereby increase the likelihood of a reading error. Eventually, the signal from the DVC2 voltage generator will restore the proper equilibrate voltage once the RAS low signal ends. Nevertheless, for purposes of detecting this problem before non-test operations begin, it would be desirable to slow the restoration of the proper Veq level.
A third example concerns a defect that could exist within the memory cell's storage capacitor, such as a defect in a nitride layer acting as a dielectric between the memory cell's conductive plates. Such a defect could cause a short within the storage capacitor. Because the storage capacitors are coupled to the DVC2 voltage generator, a defective capacitor “storing” a 0 volt charge, representing a logic 0, will slowly charge to the DVC2 level. The closer the storage capacitor approaches a DVC2 charge, the more likely that a logic 1 value may be misread during the next reading. One way to detect this problem in the prior art is to initiate a static refresh pause, wherein the memory cell's access transistor remains deactivated for a longer time than usual—generally 100 milliseconds. As a result, the capacitor, which should be storing a logic 0, has a longer time to charge to a higher voltage, thereby making an error in the next reading cycle more likely.
Once again, a speedier test is desired. The defect might be detected earlier if the problem were exacerbated to the point where the leaked charge for the stored logic 0 exceeded the equilibrate charge of the digit lines. As a result, a logic 1 would be read from the cell even though it was known that a logic 0 had been written. One could speed up the leakage into the storage capacitor by forcing DVC2 to a higher voltage. However, the equilibrate voltage of the digit lines would also increase accordingly and remain higher than the voltage of the charge in the storage capacitor. Thus, forcing DVC2 would not appreciably increase the ability to detect an error unless the equilibration of the digit lines could be slowed. The only way to do this in the prior art is through the use of a costly metal option to change the gate voltage of the bleeder device.